# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (UFS, SC8280XP)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  The QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    enum:
      - qcom,sc8280xp-qmp-ufs-phy
      - qcom,sm6125-qmp-ufs-phy
      - qcom,sm8550-qmp-ufs-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: ref
      - const: ref_aux

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: ufsphy

  vdda-phy-supply: true

  vdda-pll-supply: true

  "#clock-cells":
    const: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

    ufs_mem_phy: phy@1d87000 {
        compatible = "qcom,sc8280xp-qmp-ufs-phy";
        reg = <0x01d87000 0x1000>;

        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
        clock-names = "ref", "ref_aux";

        power-domains = <&gcc UFS_PHY_GDSC>;

        resets = <&ufs_mem_hc 0>;
        reset-names = "ufsphy";

        vdda-phy-supply = <&vreg_l6b>;
        vdda-pll-supply = <&vreg_l3b>;

        #phy-cells = <0>;
    };
